MySensors Library & Examples
2.3.1
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The values here are designed to be passed to various functions in the bcm2835 library.
Variables | |
uint32_t * | bcm2835_peripherals_base |
uint32_t | bcm2835_peripherals_size |
uint32_t * | bcm2835_peripherals |
volatile uint32_t * | bcm2835_st |
volatile uint32_t * | bcm2835_gpio |
volatile uint32_t * | bcm2835_pwm |
volatile uint32_t * | bcm2835_clk |
volatile uint32_t * | bcm2835_pads |
volatile uint32_t * | bcm2835_spi0 |
volatile uint32_t * | bcm2835_bsc0 |
volatile uint32_t * | bcm2835_bsc1 |
#define BCM2835_BLOCK_SIZE (4*1024) |
Size of memory block on RPi
#define BCM2835_BSC0_BASE 0x205000 |
Base Address of the BSC0 registers
#define BCM2835_BSC1_BASE 0x804000 |
Base Address of the BSC1 registers
#define BCM2835_BSC_A 0x000c |
BSC Master Slave Address
#define BCM2835_BSC_C 0x0000 |
BSC Master Control
#define BCM2835_BSC_C_CLEAR_1 0x00000020 |
Clear FIFO Clear
#define BCM2835_BSC_C_CLEAR_2 0x00000010 |
Clear FIFO Clear
#define BCM2835_BSC_C_I2CEN 0x00008000 |
I2C Enable, 0 = disabled, 1 = enabled
#define BCM2835_BSC_C_INTD 0x00000100 |
Interrupt on DONE
#define BCM2835_BSC_C_INTR 0x00000400 |
Interrupt on RX
#define BCM2835_BSC_C_INTT 0x00000200 |
Interrupt on TX
#define BCM2835_BSC_C_READ 0x00000001 |
Read transfer
#define BCM2835_BSC_C_ST 0x00000080 |
Start transfer, 1 = Start a new transfer
#define BCM2835_BSC_CLKT 0x001c |
BSC Master Clock Stretch Timeout
#define BCM2835_BSC_DEL 0x0018 |
BSC Master Data Delay
#define BCM2835_BSC_DIV 0x0014 |
BSC Master Clock Divider
#define BCM2835_BSC_DLEN 0x0008 |
BSC Master Data Length
#define BCM2835_BSC_FIFO 0x0010 |
BSC Master Data FIFO
#define BCM2835_BSC_FIFO_SIZE 16 |
BSC FIFO size
#define BCM2835_BSC_S 0x0004 |
BSC Master Status
#define BCM2835_BSC_S_CLKT 0x00000200 |
Clock stretch timeout
#define BCM2835_BSC_S_DONE 0x00000002 |
Transfer DONE
#define BCM2835_BSC_S_ERR 0x00000100 |
ACK error
#define BCM2835_BSC_S_RXD 0x00000020 |
RXD FIFO contains data
#define BCM2835_BSC_S_RXF 0x00000080 |
RXF FIFO full, 0 = FIFO is not full, 1 = FIFO is full
#define BCM2835_BSC_S_RXR 0x00000008 |
RXR FIFO needs reading (full)
#define BCM2835_BSC_S_TA 0x00000001 |
Transfer Active
#define BCM2835_BSC_S_TXD 0x00000010 |
TXD FIFO can accept data
#define BCM2835_BSC_S_TXE 0x00000040 |
TXE FIFO full, 0 = FIFO is not full, 1 = FIFO is full
#define BCM2835_BSC_S_TXW 0x00000004 |
TXW FIFO needs writing (full)
#define BCM2835_CLOCK_BASE 0x101000 |
Base Address of the Clock/timer registers
#define BCM2835_CORE_CLK_HZ 250000000 |
Speed of the core clock core_clk 250 MHz
#define BCM2835_GPAFEN0 0x0088 |
GPIO Pin Async. Falling Edge Detect 0
#define BCM2835_GPAFEN1 0x008c |
GPIO Pin Async. Falling Edge Detect 1
#define BCM2835_GPAREN0 0x007c |
GPIO Pin Async. Rising Edge Detect 0
#define BCM2835_GPAREN1 0x0080 |
GPIO Pin Async. Rising Edge Detect 1
#define BCM2835_GPCLR0 0x0028 |
GPIO Pin Output Clear 0
#define BCM2835_GPCLR1 0x002c |
GPIO Pin Output Clear 1
#define BCM2835_GPEDS0 0x0040 |
GPIO Pin Event Detect Status 0
#define BCM2835_GPEDS1 0x0044 |
GPIO Pin Event Detect Status 1
#define BCM2835_GPFEN0 0x0058 |
GPIO Pin Falling Edge Detect Enable 0
#define BCM2835_GPFEN1 0x005c |
GPIO Pin Falling Edge Detect Enable 1
#define BCM2835_GPFSEL0 0x0000 |
GPIO register offsets from BCM2835_GPIO_BASE. Offsets into the GPIO Peripheral block in bytes per 6.1 Register ViewGPIO Function Select 0
#define BCM2835_GPFSEL1 0x0004 |
GPIO Function Select 1
#define BCM2835_GPFSEL2 0x0008 |
GPIO Function Select 2
#define BCM2835_GPFSEL3 0x000c |
GPIO Function Select 3
#define BCM2835_GPFSEL4 0x0010 |
GPIO Function Select 4
#define BCM2835_GPFSEL5 0x0014 |
GPIO Function Select 5
#define BCM2835_GPHEN0 0x0064 |
GPIO Pin High Detect Enable 0
#define BCM2835_GPHEN1 0x0068 |
GPIO Pin High Detect Enable 1
#define BCM2835_GPIO_BASE 0x200000 |
Base Address of the GPIO registers
#define BCM2835_GPIO_PADS 0x100000 |
Base Address of the Pads registers
#define BCM2835_GPIO_PWM 0x20C000 |
Base Address of the PWM registers
#define BCM2835_GPLEN0 0x0070 |
GPIO Pin Low Detect Enable 0
#define BCM2835_GPLEN1 0x0074 |
GPIO Pin Low Detect Enable 1
#define BCM2835_GPLEV0 0x0034 |
GPIO Pin Level 0
#define BCM2835_GPLEV1 0x0038 |
GPIO Pin Level 1
#define BCM2835_GPPUD 0x0094 |
GPIO Pin Pull-up/down Enable
#define BCM2835_GPPUDCLK0 0x0098 |
GPIO Pin Pull-up/down Enable Clock 0
#define BCM2835_GPPUDCLK1 0x009c |
GPIO Pin Pull-up/down Enable Clock 1
#define BCM2835_GPREN0 0x004c |
GPIO Pin Rising Edge Detect Enable 0
#define BCM2835_GPREN1 0x0050 |
GPIO Pin Rising Edge Detect Enable 1
#define BCM2835_GPSET0 0x001c |
GPIO Pin Output Set 0
#define BCM2835_GPSET1 0x0020 |
GPIO Pin Output Set 1
#define BCM2835_PAD_DRIVE_10mA 0x04 |
10mA drive current
#define BCM2835_PAD_DRIVE_12mA 0x05 |
12mA drive current
#define BCM2835_PAD_DRIVE_14mA 0x06 |
14mA drive current
#define BCM2835_PAD_DRIVE_16mA 0x07 |
16mA drive current
#define BCM2835_PAD_DRIVE_2mA 0x00 |
2mA drive current
#define BCM2835_PAD_DRIVE_4mA 0x01 |
4mA drive current
#define BCM2835_PAD_DRIVE_6mA 0x02 |
6mA drive current
#define BCM2835_PAD_DRIVE_8mA 0x03 |
8mA drive current
#define BCM2835_PAD_HYSTERESIS_ENABLED 0x08 |
Hysteresis enabled
#define BCM2835_PAD_PASSWRD (0x5A << 24) |
Pad Control masks Password to enable setting pad mask
#define BCM2835_PAD_SLEW_RATE_UNLIMITED 0x10 |
Slew rate unlimited
#define BCM2835_PADS_GPIO_0_27 0x002c |
Pad control register offsets from BCM2835_GPIO_PADS Pad control register for pads 0 to 27
#define BCM2835_PADS_GPIO_28_45 0x0030 |
Pad control register for pads 28 to 45
#define BCM2835_PADS_GPIO_46_53 0x0034 |
Pad control register for pads 46 to 53
#define BCM2835_PAGE_SIZE (4*1024) |
Size of memory page on RPi
#define BCM2835_PERI_BASE 0x20000000 |
Physical addresses for various peripheral register sets Base Physical Address of the BCM 2835 peripheral registers Note this is different for the RPi2 BCM2836, where this is derived from /proc/device-tree/soc/ranges If /proc/device-tree/soc/ranges exists on a RPi 1 OS, it would be expected to contain the following numbers:
Peripherals block base address on RPi 1
#define BCM2835_PERI_SIZE 0x01000000 |
Size of the peripherals block on RPi 1
#define BCM2835_PWM0_DATA 5 |
PWM Channel 0 Data
#define BCM2835_PWM0_ENABLE 0x0001 |
Channel Enable
#define BCM2835_PWM0_MS_MODE 0x0080 |
Run in Mark/Space mode
#define BCM2835_PWM0_OFFSTATE 0x0008 |
Ouput Off state
#define BCM2835_PWM0_RANGE 4 |
PWM Channel 0 Range
#define BCM2835_PWM0_REPEATFF 0x0004 |
Repeat last value if FIFO empty
#define BCM2835_PWM0_REVPOLAR 0x0010 |
Reverse polarity
#define BCM2835_PWM0_SERIAL 0x0002 |
Run in serial mode
#define BCM2835_PWM0_USEFIFO 0x0020 |
Data from FIFO
#define BCM2835_PWM1_DATA 9 |
PWM Channel 1 Data
#define BCM2835_PWM1_ENABLE 0x0100 |
Channel Enable
#define BCM2835_PWM1_MS_MODE 0x8000 |
Run in Mark/Space mode
#define BCM2835_PWM1_OFFSTATE 0x0800 |
Ouput Off state
#define BCM2835_PWM1_RANGE 8 |
PWM Channel 1 Range
#define BCM2835_PWM1_REPEATFF 0x0400 |
Repeat last value if FIFO empty
#define BCM2835_PWM1_REVPOLAR 0x1000 |
Reverse polarity
#define BCM2835_PWM1_SERIAL 0x0200 |
Run in serial mode
#define BCM2835_PWM1_USEFIFO 0x2000 |
Data from FIFO
#define BCM2835_PWM_CLEAR_FIFO 0x0040 |
Clear FIFO
#define BCM2835_PWM_CONTROL 0 |
PWM Control register
#define BCM2835_PWM_DMAC 2 |
PWM DMA Configuration
#define BCM2835_PWM_FIF1 6 |
PWM FIFO Input
#define BCM2835_PWM_PASSWRD (0x5A << 24) |
Password to enable setting PWM clock
#define BCM2835_PWM_STATUS 1 |
PWM Status register
#define BCM2835_PWMCLK_CNTL 40 |
PWM Clock Control
#define BCM2835_PWMCLK_DIV 41 |
PWM Clock Divider
#define BCM2835_SPI0_BASE 0x204000 |
Base Address of the SPI0 registers
#define BCM2835_SPI0_CLK 0x0008 |
SPI Master Clock Divider
#define BCM2835_SPI0_CS 0x0000 |
SPI Master Control and Status
#define BCM2835_SPI0_CS_ADCS 0x00000800 |
ADCS Automatically Deassert Chip Select
#define BCM2835_SPI0_CS_CLEAR 0x00000030 |
Clear FIFO Clear RX and TX
#define BCM2835_SPI0_CS_CLEAR_RX 0x00000020 |
Clear FIFO Clear RX
#define BCM2835_SPI0_CS_CLEAR_TX 0x00000010 |
Clear FIFO Clear TX
#define BCM2835_SPI0_CS_CPHA 0x00000004 |
Clock Phase
#define BCM2835_SPI0_CS_CPOL 0x00000008 |
Clock Polarity
#define BCM2835_SPI0_CS_CS 0x00000003 |
Chip Select
#define BCM2835_SPI0_CS_CSPOL 0x00000040 |
Chip Select Polarity
#define BCM2835_SPI0_CS_CSPOL0 0x00200000 |
Chip Select 0 Polarity
#define BCM2835_SPI0_CS_CSPOL1 0x00400000 |
Chip Select 1 Polarity
#define BCM2835_SPI0_CS_CSPOL2 0x00800000 |
Chip Select 2 Polarity
#define BCM2835_SPI0_CS_DMA_LEN 0x01000000 |
Enable DMA mode in Lossi mode
#define BCM2835_SPI0_CS_DMAEN 0x00000100 |
DMAEN DMA Enable
#define BCM2835_SPI0_CS_DONE 0x00010000 |
Done transfer Done
#define BCM2835_SPI0_CS_INTD 0x00000200 |
INTD Interrupt on Done
#define BCM2835_SPI0_CS_INTR 0x00000400 |
INTR Interrupt on RXR
#define BCM2835_SPI0_CS_LEN 0x00002000 |
LEN LoSSI enable
#define BCM2835_SPI0_CS_LEN_LONG 0x02000000 |
Enable Long data word in Lossi mode if DMA_LEN is set
#define BCM2835_SPI0_CS_LMONO 0x00004000 |
Unused
#define BCM2835_SPI0_CS_REN 0x00001000 |
REN Read Enable
#define BCM2835_SPI0_CS_RXD 0x00020000 |
RXD RX FIFO contains Data
#define BCM2835_SPI0_CS_RXF 0x00100000 |
RXF - RX FIFO Full
#define BCM2835_SPI0_CS_RXR 0x00080000 |
RXR RX FIFO needs Reading (full)
#define BCM2835_SPI0_CS_TA 0x00000080 |
Transfer Active
#define BCM2835_SPI0_CS_TE_EN 0x00008000 |
Unused
#define BCM2835_SPI0_CS_TXD 0x00040000 |
TXD TX FIFO can accept Data
#define BCM2835_SPI0_DC 0x0014 |
SPI DMA DREQ Controls
#define BCM2835_SPI0_DLEN 0x000c |
SPI Master Data Length
#define BCM2835_SPI0_FIFO 0x0004 |
SPI Master TX and RX FIFOs
#define BCM2835_SPI0_LTOH 0x0010 |
SPI LOSSI mode TOH
#define BCM2835_ST_BASE 0x3000 |
Offsets for the bases of various peripherals within the peripherals block / Base Address of the System Timer registers
#define BCM2835_ST_CHI 0x0008 |
System Timer Counter Upper 32 bits
#define BCM2835_ST_CLO 0x0004 |
System Timer Counter Lower 32 bits
#define BCM2835_ST_CS 0x0000 |
System Timer Control/Status
#define BMC2835_RPI2_DT_FILENAME "/proc/device-tree/soc/ranges" |
On RPi2 with BCM2836, and all recent OSs, the base of the peripherals is read from a /proc file
#define BMC2835_RPI2_DT_PERI_BASE_ADDRESS_OFFSET 4 |
Offset into BMC2835_RPI2_DT_FILENAME for the peripherals base address
#define BMC2835_RPI2_DT_PERI_SIZE_OFFSET 8 |
Offset into BMC2835_RPI2_DT_FILENAME for the peripherals size address
#define HIGH 0x1 |
This means pin HIGH, true, 3.3volts on a pin.
#define LOW 0x0 |
This means pin LOW, false, 0volts on a pin.
bcm2835PortFunction Port function select modes for bcm2835_gpio_fsel()
bcm2835I2CClockDivider Specifies the divider used to generate the I2C clock from the system clock. Clock divided is based on nominal base clock rate of 250MHz
bcm2835I2CReasonCodes Specifies the reason codes for the bcm2835_i2c_write and bcm2835_i2c_read functions.
enum bcm2835PadGroup |
bcm2835PadGroup Pad group specification for bcm2835_gpio_pad()
Enumerator | |
---|---|
BCM2835_PAD_GROUP_GPIO_0_27 |
Pad group for GPIO pads 0 to 27 |
BCM2835_PAD_GROUP_GPIO_28_45 |
Pad group for GPIO pads 28 to 45 |
BCM2835_PAD_GROUP_GPIO_46_53 |
Pad group for GPIO pads 46 to 53 |
enum bcm2835PUDControl |
bcm2835PUDControl Pullup/Pulldown defines for bcm2835_gpio_pud()
Enumerator | |
---|---|
BCM2835_GPIO_PUD_OFF |
Off ? disable pull-up/down 0b00 |
BCM2835_GPIO_PUD_DOWN |
Enable Pull Down control 0b01 |
BCM2835_GPIO_PUD_UP |
Enable Pull Up control 0b10 |
bcm2835PWMClockDivider Specifies the divider used to generate the PWM clock from the system clock. Figures below give the divider, clock period and clock frequency. Clock divided is based on nominal PWM base clock rate of 19.2MHz The frequencies shown for each divider have been confirmed by measurement
enum bcm2835RegisterBase |
bcm2835RegisterBase Register bases for bcm2835_regbase()
enum bcm2835SPIBitOrder |
bcm2835SPIBitOrder SPI Bit order Specifies the SPI data bit ordering for bcm2835_spi_setBitOrder()
Enumerator | |
---|---|
BCM2835_SPI_BIT_ORDER_LSBFIRST |
LSB First |
BCM2835_SPI_BIT_ORDER_MSBFIRST |
MSB First |
enum bcm2835SPIChipSelect |
bcm2835SPIClockDivider Specifies the divider used to generate the SPI clock from the system clock. Figures below give the divider, clock period and clock frequency. Clock divided is based on nominal base clock rate of 250MHz It is reported that (contrary to the documentation) any even divider may used. The frequencies shown for each divider have been confirmed by measurement.
enum bcm2835SPIMode |
SPI Data mode Specify the SPI data mode to be passed to bcm2835_spi_setDataMode()
Enumerator | |
---|---|
BCM2835_SPI_MODE0 |
CPOL = 0, CPHA = 0 |
BCM2835_SPI_MODE1 |
CPOL = 0, CPHA = 1 |
BCM2835_SPI_MODE2 |
CPOL = 1, CPHA = 0 |
BCM2835_SPI_MODE3 |
CPOL = 1, CPHA = 1 |
enum RPiGPIOPin |
GPIO Pin Numbers.
Here we define Raspberry Pin GPIO pins on P1 in terms of the underlying BCM GPIO pin numbers. These can be passed as a pin number to any function requiring a pin. Not all pins on the RPi 26 bin IDE plug are connected to GPIO pins and some can adopt an alternate function. RPi version 2 has some slightly different pinouts, and these are values RPI_V2_*. RPi B+ has yet differnet pinouts and these are defined in RPI_BPLUS_*. At bootup, pins 8 and 10 are set to UART0_TXD, UART0_RXD (ie the alt0 function) respectively When SPI0 is in use (ie after bcm2835_spi_begin()), SPI0 pins are dedicated to SPI and cant be controlled independently. If you are using the RPi Compute Module, just use the GPIO number: there is no need to use one of these symbolic names
volatile uint32_t* bcm2835_bsc0 |
Base of the BSC0 registers. Available after bcm2835_init has been called (as root)
volatile uint32_t* bcm2835_bsc1 |
Base of the BSC1 registers. Available after bcm2835_init has been called (as root)
volatile uint32_t* bcm2835_clk |
Base of the CLK registers. Available after bcm2835_init has been called (as root)
volatile uint32_t* bcm2835_gpio |
Base of the GPIO registers. Available after bcm2835_init has been called
volatile uint32_t* bcm2835_pads |
Base of the PADS registers. Available after bcm2835_init has been called (as root)
uint32_t* bcm2835_peripherals |
Virtual memory address of the mapped peripherals block
uint32_t* bcm2835_peripherals_base |
Physical address and size of the peripherals block May be overridden on RPi2
uint32_t bcm2835_peripherals_size |
Size of the peripherals block to be mapped
volatile uint32_t* bcm2835_pwm |
Base of the PWM registers. Available after bcm2835_init has been called (as root)
volatile uint32_t* bcm2835_spi0 |
Base of the SPI0 registers. Available after bcm2835_init has been called (as root)
volatile uint32_t* bcm2835_st |
Base of the ST (System Timer) registers. Available after bcm2835_init has been called (as root)